The present invention relates in general to integrated circuit chips, and in particular, to chips designed for multi-chip systems, especially to aspects of packaging, layout and inter-chip communication aspects of such chips.
Operating speeds of integrated circuits, e.g., xe2x80x9cIC chipsxe2x80x9d, are ever increasing. Furthermore, according to another trend, chips with extremely dense circuitry and input and output (xe2x80x9ci/oxe2x80x9d) traffic are being implemented on one chip and are being packaged as high-speed, multi-chip systems. High-speed processor chips are an example of this trend. These developments lead to a need to transmit signals between chips at high speeds.
There is a potential to improve communication and operating speeds by locating chips, and especially their i/o leads, close to one another. However, the layout of these very dense chips and their i/o leads is a very complicated matter, making it difficult to design features in their layout which permit such chips to be packaged close to one another.
As a result, there is a need in the art for improvements in chip and package layout, as well as inter-chip communication methods, in order to address the foregoing needs.
The forgoing needs are met, in at least some respects, in the following methods of communicating among chips coupled in a communication ring on a multi-chip module.
A signal is transmitted from a sending chip to a first receiving chip in the communications ring via a first i/o set of the sending chip. A signal from the sending chip to a second receiving chip in the communications ring is transmitted via a second i/o set of the sending chip. The first i/o set corresponds to a first direction for the sending chip around the ring, and the second i/o set corresponds to a second direction for the sending chip around the ring. The transmitting via the first i/o set is for a circumstance where a number of chips interposed in the ring between the sending and receiving chips in the first direction is not greater than the number of chips interposed in the second direction. The transmitting via the second i/o set is for a circumstance where a number of chips interposed in the ring between the sending and receiving chips in the first direction is greater than a number of interposed chips in the second direction.
For the circumstance where there is at least one interposed chip, the transmitting includes the signal traversing from one of the first and second i/o sets of the at least one interposed chip, to the other one of the first and second i/o sets of the at least one interposed chip.
In one aspect, the transmitting of the signal via the first i/o set includes transmitting the signal via a first i/o subset of the first i/o set for a circumstance where the number of intervening chips in the first direction is less than a certain limit, and via a second i/o subset of the first i/o set for a circumstance where the number of intervening chips in the first direction is not less than the certain limit.
In another aspect, the signal traversing from one of the first and second i/o sets of the at least one interposed chip, to the other one of the first and second i/o sets of the at least one interposed chip includes the signal being regenerated.
In another embodiment, a method is disclosed for communicating among chips coupled in a communication ring on a multi-chip module, where the communication ring has a first and second direction aroiund the ring, and the respective chips have first and second i/o sets corresponding to the respective directions. A signal is transmitted to a receiving chip in the communication ring via the second i/o set of a sending chip in the communications ring, for a circumstance where a number of intervening chips in the first direction is greater than a number of intervening chips in the second direction. Alternatively, the signal is transmitted to the receiving chip via the first i/o set of the sending one of the chips, for the circumstance where the number of intervening chips in the first direction is not greater than the number of intervening chips in the second direction.
In another aspect, for the circumstance where there is at least one interposed chip, the transmitting includes the signal traversing from one of the first and second i/o sets of the at least one interposed chip, to the other one of the first and second i/o sets of the at least one interposed chip.
For the alternative where the transmitting is by the first i/o set, for example, the signal is transmitted via a first i/o subset of the first i/o set for a circumstance where the number of intervening chips in the first direction is less than a certain limit, and via a second i/o subset of the first i/o set for a circumstance where the number of intervening chips in the first direction is not less than the certain limit.
In another aspect, the signal traversing from one of the first and second i/o sets of the at least one interposed chip, to the other one of the first and second i/o sets of the at least one interposed chip includes the signal being regenerated.